Xilong Xie

Xilong Xie

Ph.D. Candidate

🚩 About Me

My name is Xilong Xie, and I am a fourth-year Ph.D. student at the School of Computer Science and Engineering, Beihang University. I am currently supervised by Prof. Limin Xiao and Prof. Liang Wang.
My research focuses on LLM serving system, hardware acceleration for LLMs. I have published several first-author/co-author papers in top conferences and journals, including MICRO, IEEE TC, DATE, TCAD, JSA, and ASP-DAC.
Feel free to reach out if you’d like to discuss research topics or collaborate!

⭐ Research Interests

LLM Hardware Accelerator: Specialized architecture designed to speed up LLM inference by optimizing both computation and memory access.
LLM Serving System Optimization: Enhancing LLM serving quality using quantization and other system-level acceleration methods.

📝 Publications

First-Author Publications

  • Xilong Xie, Liang Wang, Limin Xiao, Meng Han, Lei Liu, Xiangrong Xu, Jinquan Wang, Zhen Song, and Xiaojian Liao. “Amove: Accelerating LLMs through Mitigating Outliers and Salient Points via Fine-Grained Grouped Vectorized Data Type” In Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture (MICRO ‘25). 🔗[Link]
  • Xilong Xie, Liang Wang, Limin Xiao, Li Ruan, Tairan Zhang, Jinquan Wang, Jinquan Wang, Yongyue Wang, and Xiaojian Liao. “Accelerating LLM Inference via Low-Bit Fine-Grained Quantization Algorithm and Bit-Level Accelerator Co-Design” In IEEE Transactions on Computers(IEEE TC), doi: 10.1109/TC.2025.3628629. 🔗[Link]
  • Xilong Xie, Liang Wang, Limin Xiao, Meng Han, Lin Sun, Shuai Zheng, Xiangrong Xu. “FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMs” In 2025 Design, Automation & Test in Europe Conference (DATE). 🔗[Link]
  • Xilong Xie, Tong Guo,Limin Xiao,Meng Han,Xiangrong Xu,Jin Dong,Liang Wang.Adversarial Patch Steganography Enhancement through Localized Style Fusion[J].Journal of Cyber Security,2025,10(5):64-76 🔗[Link]

Co-Authored Publications

  • Meng Han, Liang Wang, Limin Xiao, Hao Zhang, Bowen Jiang, Xilong Xie, Jianfeng Zhu, Shaojun Wei, and Leibo Liu. “PointISA: ISA-Extensions for Efficient Point Cloud Analytics via Architecture and Algorithm Co-Design” In Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture (MICRO ‘25). 🔗[Link]
  • Xiangrong Xu, Liang Wang, Limin Xiao, Lei Liu, Yuanqiu Lv, Xilong Xie, Meng Han, and Hao Liu . “ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), vol. 43, no. 5, pp. 1429-1441, May 2024, doi: 10.1109/TCAD.2023.3337192. 🔗[Link]
  • Meng Han, Liang Wang, Limin Xiao, Hao Zhang, Chenhao Zhang, Xilong Xie, Shuai Zheng, and Jin Dong. “FuseFPS: Accelerating Farthest Point Sampling with Fusing KD-tree Construction for Point Clouds” In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC). 🔗[Link]
  • Xiangrong Xu, Liang Wang, Limin Xiao, Lei Liu, Zihao Zhou, Yuanqiu Lv, Li Ruan, Xilong Xie, Meng Han, and Xiaojian Liao. “Exploiting intra-chip locality for multi-chip GPUs via two-level shared L1 cache.” Journal of Systems Architecture (JSA), vol. 167, art. 103500, 2025. 🔗[Link]
  • Shuai Zheng, Xiangrong Xu, Limin Xiao, Hao Liu, Xilong Xie, Rui Yang, Li Ruan, Xiaojian Liao, Shanfeng Liu, Wancai Zhang, WANG Liang. Mitigating Cache Side-channel Attacks via Fast Flushing Mechanism[J]. Journal of Electronics & Information Technology, 2025, 47(9): 3178-3186. doi: 10.11999/JEIT250471. 🔗[Link]

Preprints

  • Jinquan Wang, Xiaojian Liao, Xuzhao Liu, Jiashun Suo, Zhisheng Huo, Chenhao Zhang, Xiangrong Xu, Runnan Shen, Xilong Xie, Limin Xiao. DeepCEE: Efficient Cross-Region Model Distributed Training System under Heterogeneous GPUs and Networks. 🔗[Arxiv]

🎓 Educations

- 2022.09 - Now, Ph.D., School of Computer Science and Engineering, Beihang University, Beijing, China.
- 2018.09 - 2022.07, B.S., School of Computer Science, China University of Petroleum (East China), Qingdao, China.